Name
Abstract | ||
|---|---|---|
A CMOS IC that implements the 802.3 Ethernet standards for 10- and 100-Mb/s data rates is described. The circuit uses mixed-signal techniques to perform transmit pulse shaping, receive adaptive line equalization, baseline wander compensation, and timing recovery. The IC occupies 23 mm/sup 2/ in a 0.6-/spl mu/m single-poly CMOS process and dissipates 850 mW from a 5-V supply. |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/4.735701 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Transceivers,Ethernet networks,Protocols,ANSI standards,Standards development,CMOS integrated circuits,FDDI,Adaptive equalizers,Timing,Coaxial cables | Journal | 33 |
Issue | ISSN | Citations |
12 | 0018-9200 | 7 |
PageRank | References | Authors |
1.38 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| J. Everitt | 1 | 7 | 1.38 |
| J. F. Parker | 2 | 7 | 1.38 |
| P. Hurst | 3 | 7 | 1.38 |
| D. Nack | 4 | 7 | 1.38 |
| K. Rao Konda | 5 | 7 | 1.38 |