Name
Title | ||
|---|---|---|
A 12×10 Gb/s fully integrated CMOS parallel optical receiver front-end amplifier array |
Abstract | ||
|---|---|---|
This paper presented a 12-channel parallel optical receiver front-end amplifier array design and realization in a low cost 0.18 μm CMOS technology.Each channel incorporated a transimpedance amplifier and a limiting amplifier.To meet the challenge for the design of high gain front-end amplifier at date rate of up to 10 Gb/s,an optimized circuit topology was proposed and some bandwidth extension technologies were adopted,including regulated cascode,shunt peaking,and active negative feedback.Against the power consump-tion,crosstalk and noise,some corresponding solutions were presented such as applying isolation structure for parallel amplifier array,and optimization of noise and circuit parameters for 10 Gb/s applications.The on-wafer measurements revealed that this chip's operation speed reached up to 10 Gb/s per channel,and 120 Gb/s with 12-channel in parallel operation.Consuming a DC power of 853 mW from a 1.8 V supply voltage,the chip exhibits a conversion gain of up to 92.6 dBΩ,and a 3 dB bandwidth of 8 GHz,the output swing and input sensitivity for a bit-error rate of 10 12 at 10 Gb/s are 310 mV and 10 mVpp,respectively.The chip size is 1142 μm×3816 μm including on-wafer testing pads. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1007/s11432-011-4385-6 | SCIENCE CHINA Information Sciences |
Keywords | Field | DocType |
parallel optical receiver,noise current,transimpedance amplifier,isolation structure,limiting amplifier,amplifier array,cmos,crosstalk | Telecommunications,Fully differential amplifier,Control theory,Operational transconductance amplifier,Direct-coupled amplifier,Instrumentation amplifier,Linear amplifier,Transimpedance amplifier,Cascade amplifier,Electrical engineering,Operational amplifier,Mathematics | Journal |
Volume | Issue | ISSN |
55 | 6 | 1869-1919 |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
4 | ||