Paper Info
Title
High-Level Synthesis in Latency Insensitive System Methodology
Abstract
This paper presents our contribution in terms of synchronization processor to a SoC design methodology based on the theory of latency insensitive systems (LIS). This methodology 1) promotes pre-developed IPs intensive reuse, 2) segments inter-IP interconnects with relay stationsto break critical paths and 3) brings robustness to data stream irregularities to IPS by encapsulation into a synchronization wrapper. Our contribution consists in IP encapsulation into a new wrapper model containing a synchronization processor, which speed and area are optimized and synthesizability guarantied. The main benejit of our approach is to preserve the local IP performances when encapsulating them. This approach is part of the RNRT ALIPTA project, which targets design automation of intensive digital signal processing systems with GA UT [l], a high-level synthesis tool.
Year
DOI
Venue
2005
10.1109/DSD.2005.47
DSD
Keywords
Field
DocType
ips intensive reuse,high-level synthesis,synchronization processor,latency insensitive system methodology,ga ut,intensive digital signal processing,design automation,ip encapsulation,new wrapper model,soc design methodology,local ip performance,synchronization wrapper,digital signal processing,system on chip,critical path,electronic design automation,design methodology,high level synthesis
Digital signal processing,Synchronization,System on a chip,Computer science,Latency (engineering),Data stream,High-level synthesis,Real-time computing,Robustness (computer science),Electronic design automation,Embedded system
Conference
ISBN
Citations 
PageRank 
0-7695-2433-8
0
0.34
References 
Authors
6
6
Name
Order
Citations
PageRank
P. Bomel121.77
N. Abdelli200.68
E. Martin300.34
A-M. Fouilliart400.68
E. Boutillon5203.37
P. Kaifasz600.34