Name
Abstract | ||
|---|---|---|
In the past two decades, the IC Design industry has set what one might refer to as milestones in the golden era of electronics and computers. Current statistics reveal that the number of gates on a chip in 2005 is 100K compared to 23K just five years back. With the chip density increasing at this rate, there is an inherent need to allow for some efficient testing mechanism on- chip to avail benefits in terms of quality as well as economy. Adding test capabilities to a chip being fabricated increases the initial infrastructure, but the savings that it brings about in terms of cost, time, and maintenance far exceeds the testing cost. In spite of all the innovations, testing asynchronous designs has remained dormant; the reason for this being its inherent complexity. Absence of the global clock signal and presence of more state-holding gates creates a more complex test environment for these designs. The motivation behind this paper stems from the requirement of an efficient testing methodology for a particular class of asynchronous circuits known as Null Conventional Logic (NCL) circuits. The methodology proposed in this paper is easy to use for testing fairly complex designs and is tailored to work with conventional DFT tools. |
Year | Venue | Keywords |
|---|---|---|
2005 | CDES | null co nventional logic,vlsi circuits,design for test,asynchronous,vlsi testing,cad tools,simulation,chip,asynchronous circuit |
Field | DocType | Citations |
Clock signal,Design for testing,Asynchronous communication,Computer architecture,Computer science,Chip,Integrated circuit design,Electronics,Very-large-scale integration,Asynchronous circuit,Reliability engineering | Conference | 0 |
PageRank | References | Authors |
0.34 | 10 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bonita Bhaskaran | 1 | 6 | 1.89 |
| Venkat Satagopan | 2 | 6 | 1.21 |
| Waleed K. Al-assadi | 3 | 17 | 5.31 |
| Scott C. Smith | 4 | 129 | 18.15 |