Name
Abstract | ||
|---|---|---|
We present a novel 4096 complex-point, fully systolic VLSI FFT architecture based on the combination of three consecutive radix-4 stages resulting in a 64-point FFT engine. The outcome of cascading these 64-point FFT engines is an improved architecture that efficiently processes large input data sets in real time. Using 64-point FFT engines reduces the buffering and the latency to one third of a fully unfolded radix-4 architecture, while the radix-4 schema simplifies the calculations within each engine. The proposed 4096 complex point architecture has been implemented on a FPGA achieving a post-route clock frequency of 200 MHz resulting in a sustained throughput of 4096 point/20.48 μs. It has also been implemented on a high performance 0.13 μm, 1P8M CMOS process achieving a worst-case (0.9 V, 125 C) post-route clock frequency of 604.5 MHz and a sustained throughput of 4096 point/3.89 μs while consuming 4.4 W. The architecture is extended to accomplish FFT computations of 16K, 64K and 256K complex points with 352, 256 and 188 MHz operating frequencies respectively. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1007/s11265-009-0364-1 | Signal Processing Systems |
Keywords | Field | DocType |
Fast Fourier transform (FFT),VLSI,FPGA,Radix-2,Radix-4,Real-time processing | Split-radix FFT algorithm,Computer science,Latency (engineering),Prime-factor FFT algorithm,Parallel computing,Field-programmable gate array,Real-time computing,Fast Fourier transform,Throughput,Computer hardware,Very-large-scale integration,Clock rate | Journal |
Volume | Issue | ISSN |
58 | 3 | 1939-8018 |
Citations | PageRank | References |
2 | 0.59 | 18 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| K. Babionitakis | 1 | 2 | 0.59 |
| v a chouliaras | 2 | 42 | 5.66 |
| Konstantinos Manolopoulos | 3 | 21 | 3.45 |
| Konstantinos Nakos | 4 | 23 | 4.46 |
| D. Reisis | 5 | 17 | 4.23 |
| N. Vlassopoulos | 6 | 5 | 1.59 |