Name
Abstract | ||
|---|---|---|
All modern hardware design makes use of hardware description languages like Verilog and VHDL. Thus these languages are presented very early in the curriculum, often in the first design course. Unfortunately, these languages often cause substantial confusion for students learning hardware design, particularly students that have experience writing programs in sequential languages like C and Java. To address this problem, we have defined a language called Abstract Verilog which is similar to Verilog, but which has well-defined, clean parallel execution semantics. Abstract Verilog has a somewhat restricted syntax in order to reduce the cognitive load for new students. However, almost any program that can be written in Verilog can be written in Abstract Verilog, where it is shorter and easier to understand. We have used Abstract Verilog successfully in both introductory and advanced design classes. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/MSE.2007.16 | MSE |
Keywords | Field | DocType |
advanced design class,cognitive load,modern hardware design,novice students,abstract verilog,design course,clean parallel execution semantics,hardware design,new student,hardware description language,restricted syntax,computational modeling,vhdl,registers,java,natural languages,computer science,parallel programming,hardware description languages | Fifth-generation programming language,Computer architecture,Second-generation programming language,Programming language,Computer science,Fourth-generation programming language,Semulation,Register-transfer level,Verilog,Third-generation programming language,Hardware description language | Conference |
ISBN | Citations | PageRank |
0-7695-2849-X | 1 | 0.43 |
References | Authors | |
1 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Carl Ebeling | 1 | 1405 | 185.32 |
| Brian French | 2 | 1 | 0.43 |