Paper Info
Title
VHDL-based design and design methodology for reusable high performance direct digital requency synthesizers
Abstract
Design methodologies for high performance Direct Digital Fre-quen--cy Synthesizers (DDFS) are described. Traditional look-up tab-les (LUT) for sine and co-sine are merged with CORDIC-inter-po---la--tion into a hybrid architecture. This implements DDFS-sys-tems with high resolution without being specific to a particular tar-get technology. Amplitude constants were obtained from ma-the-matical trigonometric functions of the IEEE math_real pack-age. These constants were then written via simulation of a VHDL model into a fully synthesizable package. Systematic and detailed studies varying the synthesizers inherent parameters lead to a design optimum of the LUT/CORDIC-ra-tio, which mini-mizes power and silicon area for a given clock frequency.
Year
DOI
Venue
2001
10.1145/378239.379026
Proceedings of the 38th annual Design Automation Conference
Keywords
Field
DocType
cordic algorithm,cy synthesizers,high resolution,design methodology,direct digital fre-quen,amplitude constant,ieee math_real pack-age,design optimization and reuse,clock frequency,detailed study,reusable high performance,vhdl-based design,direct frequency synthesis,high performance,vhdl model,direct digital requency synthesizers,hdl-based design,hardware description languages,interpolation,packaging,integrated circuit design,silicon,direct digital synthesis,look up tables,languages,design optimization,design,look up table,algorithm design and analysis
Lookup table,Trigonometric functions,Computer science,Electronic engineering,CORDIC,Integrated circuit design,VHDL,Direct digital synthesizer,Clock rate,Hardware description language
Conference
ISSN
ISBN
Citations 
0738-100X
1-58113-297-2
2
PageRank 
References 
Authors
0.42
2
3
Name
Order
Citations
PageRank
Ireneusz Janiszewski121.10
Bernhard Hoppe232.16
Hermann Meuth312538.64