Paper Info
Title
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics
Abstract
This paper presents an 8.69 Mvertices/s, 278 Mpixels/s, 15.7 mm2 tiled-based 3D graphics SoC HW/SW supporting OpenGL ES 1.0 running at 139 MHz. The SoC also includes embedded circuitry to monitor run time characteristics, detect bus protocol error/inefficiency, and capture bus traces at various abstraction levels with compression ratio up to 98%.
Year
DOI
Venue
2009
10.1109/ASPDAC.2009.4796467
ASP-DAC
Keywords
Field
DocType
bus trace,compression ratio,bus protocol error,embedded circuitry,graphics soc hw,sw development,opengl es 1.0,consumer electronics,opengl es,computer graphics,various abstraction level,time characteristic,system-on-chip,hardware-software codesign,tile-based 3d graphics soc hw-sw development,frequency 139 mhz,engines,system on chip,debugging,pixel,system on a chip,hardware,3d graphics
3D computer graphics,Computer science,Real-time computing,Electronic engineering,Electronics,Computer hardware,Tile,Computer graphics,Protocol Error,System on a chip,Compression ratio,Debugging,Embedded system
Conference
ISBN
Citations 
PageRank 
978-1-4244-2749-9
2
0.50
References 
Authors
1
10
Name
Order
Citations
PageRank
Liang-Bi Chen12618.40
Ruei-Ting Gu241.59
Wei-Sheng Huang320.50
Chien-Chou WANG420.84
Wen-Chi Shiue5101.36
Tsung-Yu Ho6162.78
Yun-Nan Chang710612.93
Shen-Fu Hsiao819931.50
Chungnan Lee959453.43
Ing-Jer Huang1020034.40