Name
Abstract | ||
|---|---|---|
A testability analysis procedure for complex analogue circuits is presented based on layout dependent fault models extracted from process defect statistics. The technique has been applied to a mixed-signal phase locked loop circuit and a number of test methodologies have been evaluated including the existing production test. It is concluded that the fault coverage achieved by this test can be improved by the use of a supplementary test based on power supply variations. |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/TEST.1994.528009 | ITC |
Keywords | Field | DocType |
layout-dependent fault models,analogue fault simulation,loop circuit,complex analogue circuit,layout dependent fault model,process defect statistic,power supply variation,supplementary test,test methodology,mixed-signal phase,fault coverage,existing production test,phase lock loop,phase locked loops,system testing,production,integrated circuit layout,vlsi,low voltage,fault model,statistical analysis | Integrated circuit layout,Stuck-at fault,Phase-locked loop,Automatic test pattern generation,Fault coverage,Computer science,System testing,Real-time computing,Electronic engineering,Low voltage,Very-large-scale integration,Reliability engineering | Conference |
ISBN | Citations | PageRank |
0-7803-2103-0 | 26 | 2.85 |
References | Authors | |
11 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| R. J. A. Harvey | 1 | 37 | 4.10 |
| Andrew M. D. Richardson | 2 | 140 | 17.91 |
| Bruls, E.M.J.G. | 3 | 138 | 13.50 |
| Keith Baker | 4 | 31 | 5.72 |