Title
An analog synchronous mirror delay for high-speed DRAM application
Abstract
An analog synchronous mirror delay (ASMD) is proposed, which provides fast locking characteristics in recovery from power-down mode in a DRAM application. As an open-loop fast locking system, ASMD measures and compensates the skew between external and internal clocks in analog operation mode within two cycles of an input clock using a charge-pumping scheme. This ASMD has no static phase error prob...
Year
DOI
Venue
1999
10.1109/4.753681
IEEE Journal of Solid-State Circuits
Keywords
DocType
Volume
Mirrors,Random access memory,Clocks,Charge pumps,CMOS technology,Current measurement,Linearity,Delay lines,Frequency,Pulse generation
Journal
34
Issue
ISSN
Citations 
4
0018-9200
6
PageRank 
References 
Authors
1.33
1
5
Name
Order
Citations
PageRank
Daeyun Shim1407.95
Dong-Yun Lee261.66
Sanghun Jung3142.41
Changhyun Kim4470151.39
Wonchan Kim5507.92