Name
Abstract | ||
|---|---|---|
In this paper, we compared previously published static Double-Edge Triggered clocked Storage Elements or double-edge-triggered flip-flops (DETFFs) for their delay, power dissipation and power delay product in 65nm CMOS technology. For each DETFF, the optimal delay, power consumption and power-delay product are determined as the primary figures of merit. Simulation results show that DETFF1 has nearly same clock to output delay as DETFF2 but DETFF1 has 93.94% and 94.27% improvement in power and PDP respectively when compared to DETFF2. DETFF3 has 31%, 57% and 69% improvement in delay, power and PDP respectively when compared to DETFF1. DETFF3 has 31.79%, 97.39% and 98.22% improvement in delay, power and PDP respectively when compared to DETFF2. DETFF2 has highest delay, highest power dissipation and so highest PDP. DETFF3 has least delay, least power dissipation and so lowest PDP. So DETFF3 is a good choice for low-power, high performance operation. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1145/2345396.2345572 | ICACCI |
Keywords | Field | DocType |
lowest pdp,highest power dissipation,power dissipation,power-delay product,highest pdp,optimal delay,power delay product,highest delay,clocked storage element,power consumption,double edge,output delay,figure of merit | Power–delay product,Computer science,Dissipation,CMOS,Electronic engineering,Figure of merit,Power consumption | Conference |
Citations | PageRank | References |
0 | 0.34 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Imran Ahmed Khan | 1 | 0 | 0.34 |
| Danish Sheikh | 2 | 0 | 0.34 |
| Mirza Tariq Beg | 3 | 10 | 2.99 |