Abstract | ||
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Sincetheintroductionofthe10GbEstandardin2002,theabilityofgeneralpurposeprocessorstoefficientlyprocessnetworktrafficwithcommonprotocolssuchasTCP/IPhasbeenrevisitedandcriticallyevaluated.However,recentcommerciallyavailableprocessorssuchasIntel®CoreTM2DuoProcessor introduce microarchitectural enhancementsthatcouldsignificantlyinfluencetheapproachtoacceleratingnetworkprocessing.WeexaminethenetworkperformanceofarealplatformcontainingIntel®CoreTMmicro-architecturebasedprocessors,the role of coherency and a prototype implementationofdirectcacheplacement(DirectCacheAccessorDCA)ofinboundnetworktraffic.Weobservethatasubstantialportionofthetimerelatestotheinefficiency of I/O specific coherence protocols in theplatform.Wedemonstratethatarelatively,lowcomplexityimplementationofDCAcalled`PrefetchHint'providesa15to43%speed-uptoreceive-sideprocessingacrossarangeofI/Osizesandpresentadetailed characterization of the benefits. |
Year | DOI | Venue |
---|---|---|
2007 | 10.1109/MICRO.2007.19 | MICRO |
Keywords | Field | DocType |
cache coherence protocols,network traffic,prototype implementationofdirectcacheplacement,microarchitectural enhancementsthatcouldsignificantlyinfluencetheapproachtoacceleratingnetworkprocessing,osizesandpresentadetailed characterization,o specific coherence protocol,protocols,network performance | Computer architecture,General purpose,Computer science,Cache,Parallel computing,Inefficiency,Real-time computing,Coherence (physics),Instruction prefetch,Network processing,Network performance,Cache coherence | Conference |
ISSN | ISBN | Citations |
1072-4451 | 0-7695-3047-8 | 100 |
PageRank | References | Authors |
3.75 | 27 | 2 |
Name | Order | Citations | PageRank |
---|---|---|---|
Amit Kumar | 1 | 156 | 13.79 |
Ram Huggahalli | 2 | 358 | 20.94 |