Name
Abstract | ||
|---|---|---|
In this paper, we propose an interconnect binding algorithm during high-level synthesis for global interconnect reduction. Our scheme is based on the observation that not all functional units (FUs) operate at all the time. When idle, FUs can be reconfigured as pass-through logic for data transfer, reducing interconnect requirement. Our algorithm formulates the interconnect reduction problem as a modified min-cost max-flow problem. It not only reduces the overall length of global interconnects but also minimizes the power overhead without introducing any timing violations. Experimental results show that, for a suite of digital processing benchmark circuits, our algorithm reduces global interconnects by 8.5% on the average in comparison to previously proposed schemes [6, 8]. It further lowers the overall design power by 4.8%. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ASPDAC.2010.5419800 | ASP-DAC |
Keywords | Field | DocType |
digital processing benchmark circuit,power overhead,functional unit,overall design power,global interconnects,reduction problem,binding algorithm,modified min-cost max-flow problem,overall length,high level synthesis,reduction technique,degradation,benchmark testing,soc,very large scale integration,computer science,algorithm design and analysis,registers,data transfer,image recognition,layout | Algorithm design,Data transmission,Computer science,Parallel computing,High-level synthesis,Real-time computing,Electronic engineering,Electronic circuit,Interconnection,Energy consumption,Very-large-scale integration,Benchmark (computing) | Conference |
ISSN | ISBN | Citations |
2153-6961 | 978-1-4244-5767-0 | 3 |
PageRank | References | Authors |
0.45 | 16 | 2 |