Abstract | ||
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Optimizing sequential cycles is essential for many types of high-performance circuits, such as pipelines for packet processing. Retiming is a powerful technique for speeding pipelines, but it is stymied by tight sequential cycles. Designers usually attack such cycles by manually combining Shannon de- composition with retiming—effectively a form of speculation—but such manual decomposition is error prone. We propose an efficient algorithm that simultaneously applies Shannon decomposition and retiming to optimize circuits with tight sequential cycles. While the algorithm is only able to improve certain circuits (roughly half of the benchmarks we tried), the performance in- crease can be dramatic (7%-61%) with only a modest increase in area (1%-12%). The algorithm is also fast, making it a practical addition to a synthesis flow. |
Year | DOI | Venue |
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2007 | 10.1109/TCAD.2006.890583 | IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
performance increase,packet processing,optimizing sequential cycles,certain circuit,tight sequential cycle,high-performance circuit,modest increase,efficient algorithm,shannon decomposition,manual decomposition,sequential cycle,feedback loop,logic,sequential circuits,indexing terms,pipelines,computer science,registers | Retiming,Pipeline transport,Sequential logic,Computer science,Parallel computing,Real-time computing,Packet processing,Electronic circuit,Decomposition | Journal |
Volume | Issue | ISSN |
26 | 3 | 0278-0070 |
ISBN | Citations | PageRank |
3-9810801-0-6 | 8 | 0.72 |
References | Authors | |
12 | 3 |
Name | Order | Citations | PageRank |
---|---|---|---|
Cristian Soviani | 1 | 10 | 1.47 |
Olivier Tardieu | 2 | 462 | 32.13 |
Stephen A. Edwards | 3 | 1443 | 109.65 |