Name
Abstract | ||
|---|---|---|
With high clock frequencies, faster transistor rise/fall time, wider wires, and the use of Cu material interconnects, interconnect inductive noise is becoming an important design metric in digital circuits. An efficient technique to reduce the inductive noise of on-chip interconnects is to insert shields among signal wires. An efficient solution for the min-area shield insertion problem to satisfy given explicit noise bounds in multiple coupled nets is provided. The proposed algorithm determines the locations and number of shields needed to satisfy certain noise constraints. Experimental results show that the proposed approach minimizes the number of shields required to satisfy the noise constraints and uses less runtime than the best alternative reported approach. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/TVLSI.2004.842882 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
efficient solution,nanometer technology,inductive noise reduction,efficient technique,certain noise constraint,on-chip interconnects,noise constraint,proposed algorithm,cu material interconnects,inductive noise,efficient shield insertion,explicit noise bound,satisfiability,chip,inductance,copper,digital circuits,nanoelectronics,noise reduction,electronic design automation,shielding,integrated circuit design,frequency | Noise reduction,Digital electronics,Fall time,Computer science,Rise time,Electronic engineering,Integrated circuit design,Shields,Transistor,Integrated circuit,Electrical engineering | Journal |
Volume | Issue | ISSN |
13 | 3 | 1063-8210 |
Citations | PageRank | References |
7 | 0.61 | 13 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mohamed A. Elgamel | 1 | 64 | 9.44 |
| Anup Kumar | 2 | 224 | 22.64 |
| Magdy A. Bayoumi | 3 | 803 | 122.04 |