Name
Abstract | ||
|---|---|---|
This paper describes a parallel implementation of the timing-driven VPR~5.0 simulated annealing engine. By restricting the move distance to a confined neighborhood, it is possible to consider a large number of non-conflicting moves in parallel and achieve a deterministic result. The full timing-driven algorithm is parallelized, including the detailed timing analysis updates done periodically while placement progresses. The limited move slightly degrades the placement quality, but this is necessary to expose greater degrees of parallelism. The overall bounding box metric degrades about 11% and critical path delay metric degrades about 8% compared to VPR's original algorithm, but we show the amount of degradation is independent of the number of threads. Overall, the parallel implementation scales to a speedup of 123x using 25 threads compared to VPR. With additional tuning effort, we believe the algorithm can be scaled to a larger number of threads, perhaps even run on a GPU, with little additional quality degradation. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/1950413.1950445 | FPGA |
Keywords | Field | DocType |
box metric degrades,timing-driven vpr,full timing-driven algorithm,parallel implementation,metric degrades,parallel implementation scale,deterministic timing-driven parallel placement,large number,larger number,additional quality degradation,original algorithm,fpga,timing analysis,simulated annealing,critical path | Simulated annealing,Computer science,Parallel computing,Field-programmable gate array,Thread (computing),Real-time computing,Critical path delay,Static timing analysis,Scalability,Speedup,Minimum bounding box | Conference |
Citations | PageRank | References |
10 | 0.79 | 26 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chris C. Wang | 1 | 10 | 1.13 |
| Guy G.F. Lemieux | 2 | 53 | 5.06 |