Name
Abstract | ||
|---|---|---|
This paper presents the EXM- algorithm, which locates multiple logic design errors in a combinational circuit with multiple output. An error possibility index and a six- valued simulation method have been introduced to reduce the number of error candidates without missing real errors. Experimental results have shown that this algorithm locates all errors at high hit ratio for benchmark circuits. (3)Indicate error location(s) exactly: what gate(s) or what line(s) are erroneous. |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1145/196244.196356 | DAC |
Keywords | Field | DocType |
multiple logic design error,multiple output circuit,combinational circuit,logic design,design automation,combinational circuits,error correction | Digital electronics,Sequential logic,Pass transistor logic,Computer science,Logic optimization,Algorithm,Combinational logic,Electronic engineering,Logic family,Register-transfer level,Asynchronous circuit | Conference |
ISSN | ISBN | Citations |
0738-100X | 0-89791-653-0 | 25 |
PageRank | References | Authors |
1.70 | 13 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masahiro Tomita | 1 | 25 | 1.70 |
| Tamotsu Yamamoto | 2 | 25 | 1.70 |
| Fuminori Sumikawa | 3 | 25 | 1.70 |
| Kotaro Hirano | 4 | 27 | 3.10 |