Paper Info
Title
On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications
Abstract
Mission-critical applications such as space or avionics increasingly demand high fault tolerance capabilities of their electronic systems. Among the fault tolerance characteristics, the performance and costs of an electronic system remain the leader factors in the space and avionics market. In particular, when considering SRAM-based FPGAs, specific hardening techniques generally based on Triple Modular Redundancy need to be adopted in order to guarantee the desired fault tolerance degree. While effectively increasing the fault tolerance capability, these techniques introduce an important performance degradation and a dramatic area overhead, that results in higher design costs. In this paper, we propose an innovative design flow that allow the implementation of fault tolerance circuits in SRAM-based FPGA devices with different fault tolerance capability degrees. We introduce a new metric that allows a designer to precisely estimate and set the desired fault tolerance capabilities. Experimental analysis performed on a realistic industrial-type case study demonstrates the efficiency of our methodology.
Year
DOI
Venue
2008
10.1145/1403375.1403456
Proceedings of the conference on Design, automation and test in Europe
Keywords
Field
DocType
triple modular redundancy,avionics,design flow,field programmable gate arrays,experimental analysis,fault tolerance,hardware acceleration,space missions,redundancy,fault tolerant,logic design
Logic synthesis,Stuck-at fault,Fault coverage,Computer science,Triple modular redundancy,Software fault tolerance,Real-time computing,Design flow,Fault tolerance,Redundancy (engineering),Embedded system
Conference
ISSN
ISBN
Citations 
1530-1591
978-3-9810801-4-8
16
PageRank 
References 
Authors
1.08
6
4
Name
Order
Citations
PageRank
Luca Sterpone123341.54
M. A. Aguirre2202.66
Jonathan Noel Tombs33513.16
Hipólito Guzmán-Miranda4566.87