Name
Abstract | ||
|---|---|---|
General purpose parallel processing machines are increasingly being used to speed up a variety of VLSI CAD applications. This paper addresses logic simulation on parallel machines by exploiting the concurrency in the circuit being simulated (called data parallelism) as opposed to exploiting parallelism inherent in the simulation algorithm itself (called functional parallelism). The most crucial step in obtaining the maximum parallelism using data parallelism is the partitioning of circuit elements. We introduce a cost function which tries to model the simulation of a logic circuit in a parallel environment. The cost function tries to estimate the parallel run time for logic simulation given the processor assignment and the underlying multiprocessor architecture. We then present different heuristic algorithms to partition the circuit and evaluate the efficiency of these algorithms using the proposed cost function. Partitioning algorithms for both event-driven and compiled code simulation are given. |
Year | DOI | Venue |
|---|---|---|
1989 | 10.1145/76263.76303 | Reno, NV, United States |
Keywords | Field | DocType |
efficient circuit,general purpose parallel processing,functional parallelism,maximum parallelism,code simulation,paper addresses logic simulation,logic simulation,cost function,circuit element,simulation algorithm,data parallelism,parallel logic simulation,parallel processing,heuristic algorithm,discrete event simulation,concurrent computing,very large scale integration,data mining,logic circuits | Logic gate,Concurrency,Computer science,Task parallelism,Parallel computing,Algorithm,Logic simulation,Data parallelism,Very-large-scale integration,Speedup,Cost efficiency | Conference |
ISBN | Citations | PageRank |
0-89791-341-8 | 8 | 0.89 |
References | Authors | |
11 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Patil, S. | 1 | 8 | 0.89 |
| Banerjee, P. | 2 | 66 | 9.21 |
| C. Polychronopoulos | 3 | 145 | 23.10 |