Name
Abstract | ||
|---|---|---|
The clock period in conventional pipeline scheme is proportional to the maximum delay while in hybrid wave-pipelining it is proportional to the maximum delay difference. An 8 脳8-bit hybrid wave-pipeline multiplier using carry-save adder technique is described. The multiplier has been designed using TSMC 180nm. The basic cells in multiplier are designed to have small propagation delay and delay variation. The hybrid wave-pipelined multiplier is able to achieve 2.86 billion multiplications per second. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ISVLSI.2005.7 | ISVLSI |
Keywords | Field | DocType |
integrated circuit design,adders,very large scale integration,uncertainty,propagation delay,carry save adder,logic,frequency | Propagation delay,Adder,Computer science,Multiplier (economics),Electronic engineering,Carry-save adder,Integrated circuit design,Very-large-scale integration | Conference |
ISSN | ISBN | Citations |
2159-3469 | 0-7695-2365-X | 1 |
PageRank | References | Authors |
0.40 | 2 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Suryanarayana Tatapudi | 1 | 8 | 1.77 |
| Jose G. Delgado-Frias | 2 | 23 | 8.75 |