Name
Abstract | ||
|---|---|---|
The traditional approach to validate analog circuits is to utilize extensive SPICE-level simulations. The main challenge of this approach is knowing when all important corner cases have been simulated. A new alternative is to utilize formal verification techniques. This paper utilizes a simple example to illustrate the potential flaws of a simulation-only based validation methodology and the potential benefits of formal verification of analog circuits. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1016/j.entcs.2006.02.018 | Electr. Notes Theor. Comput. Sci. |
Keywords | Field | DocType |
traditional approach,hybrid petri nets,analog circuits,potential flaw,potential benefit,analog circuit verification,formal verification,extensive spice-level simulation,analog circuit,formal veriflcation,formal verification technique,new alternative,important corner case,main challenge | Analogue electronics,Computer science,Theoretical computer science,Formal verification | Journal |
Volume | Issue | ISSN |
153 | 3 | Electronic Notes in Theoretical Computer Science |
Citations | PageRank | References |
12 | 0.85 | 15 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chris J. Myers | 1 | 607 | 75.73 |
| Reid R Harrison | 2 | 222 | 57.49 |
| David Walter | 3 | 98 | 5.38 |
| Nicholas Seegmiller | 4 | 59 | 3.35 |
| Scott Little | 5 | 132 | 9.42 |