Name
Abstract | ||
|---|---|---|
Finite state machine (FSM) partitioning proves effective for power optimization. In this paper we propose a design model based on mixed synchronous/asynchronous state memory that results in implementations with low power dissipation and low area overhead for partitioned FSMs. The state memory here is composed of the synchronous local state memory and asynchronous global state memory, where the former is used to distinguish the states inside a sub-FSM, and the latter is responsible for controlling sub-FSM communication. The input and output behaviour of the decomposed FSM is cycle by cycle equivalent to the undecomposed synchronous FSM. Together with clock gating technique, substantial power reduction can be demonstrated. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/DSD.2004.1333298 | DSD |
Keywords | Field | DocType |
finite state machines,mixed synchronous state memory,power optimization,synchronous local state memory,finite state machine,asynchronous global state memory,circuit optimisation,undecomposed synchronous fsm,low-power electronics,fsm partitioning,logic partitioning,low power fsm design,sub-fsm communication,clock gating,heterogenous parallel,complex systems-on-a-chip,mixed asynchronous state memory,asynchronous circuits,asynchronous state memory,mixed synchronous,low power electronics | Asynchronous communication,Clock gating,Power optimization,Computer science,Dissipation,Parallel computing,Finite-state machine,Real-time computing,Input/output,Synchronous circuit,Low-power electronics | Conference |
ISBN | Citations | PageRank |
0-7695-2203-3 | 4 | 0.44 |
References | Authors | |
6 | 2 | |