Name
Abstract | ||
|---|---|---|
In this paper, we propose a new cryptographic system based on the Shannon product theory. Analysis shows it has high security. Regarding real-time applications, a five-stage pipeline architecture has been designed, implemented, and verified based on a UMC 0.18 μm CMOS technology. The simulation result shows that the proposed design achieves a throughput rates of the encryption part up to 2.79 Gbps at a silicon area cost of of 225360 μm2 and a power consumption of 16.93 mW. A comparison shows that the performance of the proposed design is much better than the existing designs. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ISCAS.2005.1466038 | ISCAS (6) |
Keywords | Field | DocType |
cmos integrated circuits,pseudorandom bit generators,2.79 gbit/s,cryptography,random number generation,multimedia cryptographic system,encryption throughput rate,shannon product theory,real-time multimedia transmission,multiple-stage pipeline architecture,cmos,16.93 mw,multimedia communication,0.18 micron,pipeline processing,throughput,pipelines,silicon,cmos technology,national security | Architecture,Multimedia transmission,Computer science,Cryptography,Electronic engineering,Encryption,CMOS,Throughput,Random number generation,Embedded system,Power consumption | Conference |
ISSN | ISBN | Citations |
0271-4302 | 0-7803-8834-8 | 2 |
PageRank | References | Authors |
0.37 | 2 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jui-Cheng Yen | 1 | 266 | 23.97 |
| Hun-Chen Chen | 2 | 108 | 11.20 |
| Shu-meng Wu | 3 | 2 | 0.37 |