Name
Abstract | ||
|---|---|---|
This paper describes a timing analysis system (ACTAS: ACcurate Timing Analysis System). This system analyzes the logical behaviors of VLSI. It verifies timings at flip-flops and detects timing errors. Then, it calculates path delays of the partial combinational circuits generating the errors. If they do not satisfy timing constraints, the system detects error paths. In this system, the former method based on behavior analysis is called DYNAMIC TIMING ANALYSIS and the latter method based on path analysis is called STATIC TIMING ANALYSIS. By use of this system, it improves the timing analysis efficiency of the complicated timing of VLSI. |
Year | DOI | Venue |
|---|---|---|
1985 | 10.1109/DAC.1985.1585927 | DAC |
Keywords | Field | DocType |
complicated timing,system detects error path,timing analysis system,static timing analysis,path analysis,accurate timing analysis system,timing constraint,behavior analysis,dynamic timing analysis,detects timing error,timing analysis efficiency,information analysis,satisfiability,timing analysis,combinational circuits,circuit analysis,logic design,combinational circuit,very large scale integration,design automation | Logic synthesis,Computer science,Electronic engineering,Real-time computing,Combinational logic,Electronic design automation,Static timing analysis,Path analysis (statistics),Network analysis,Very-large-scale integration | Conference |
ISSN | ISBN | Citations |
0738-100X | 0-8186-0635-5 | 6 |
PageRank | References | Authors |
1.14 | 3 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michiaki Muraoka | 1 | 40 | 7.50 |
| Iida, H. | 2 | 20 | 4.70 |
| Hideyuki Kikuchihara | 3 | 7 | 2.85 |
| Michio Murakami | 4 | 6 | 1.48 |
| Kazuyuki Hirakawa | 5 | 7 | 2.48 |