Name
Abstract | ||
|---|---|---|
This brief presents a method for constructing block-circulant (BC) Reed–Solomon-based low-density parity-check (RS-LDPC) codes and an efficient decoder design. The proposed construction method results in a BC form of a parity-check matrix from a random parity-check matrix for RS-LDPC codes. A decoder architecture and switch network for BC-RS-LDPC code are then developed based on the new BC parity-check matrix. Thus, an efficient decoder architecture dedicated to a promising class of high-performance BC-RS-LDPC codes is presented for the first time. Moreover, a (2048, 1723) BC-RS-LDPC decoder architecture is designed to demonstrate the efficiency of the presented techniques. Synthesis results show that the proposed decoder requires 1.3-M gates and can operate at 450 MHz to achieve a data throughput of 41 Gb/s with eight iterations. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TVLSI.2012.2210452 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
sparse matrices,throughput,switch network,iteration,decoding,logic gates,belief propagation,iterative methods,vectors | Multidimensional parity-check code,Hamming code,Concatenated error correction code,Computer science,Low-density parity-check code,Parallel computing,Block code,Arithmetic,Electronic engineering,Raptor code,Soft-decision decoder,Linear code | Journal |
Volume | Issue | ISSN |
21 | 7 | 1063-8210 |
Citations | PageRank | References |
4 | 0.41 | 8 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seong-In Hwang | 1 | 17 | 2.05 |
| Hanho Lee | 2 | 205 | 40.92 |