Name
Abstract | ||
|---|---|---|
As interconnect delays begin to dominate logic delays in large circuits, pipelined interconnects will be needed to achieve the highest performance. In FPGAs, this pipelining will be provided by the configurable interconnect architecture itself This changes the routing problem substantially since the shortest path problem, which is at the core of any router, becomes NP-hard when latency constraints are added. That is, if signals must be routed through a given number of registers between source and destination, an efficient shortest path algorithm like Djikstra's algorithm is no longer an option. We propose here an approximate algorithm that uses simple heuristics to solve the pipelined shortest path problem efficiently. We have incorporated QuickRoute in the PathFinder router to route pipelined interconnects. We present the results achieved with QuickRoute for several circuits with heavily pipelined interconnect which show an improvement over a previously described algorithm. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/FPT.2004.1393253 | 2004 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, PROCEEDINGS |
Keywords | Field | DocType |
logic design,circuit complexity,network routing,shortest path problem,field programmable gate arrays,shortest path algorithm | Equal-cost multi-path routing,Link-state routing protocol,Shortest path problem,Path vector protocol,Static routing,Computer science,Parallel computing,Constrained Shortest Path First,Real-time computing,Private Network-to-Network Interface,Dijkstra's algorithm | Conference |
Citations | PageRank | References |
6 | 0.61 | 13 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| S. Li | 1 | 6 | 0.61 |
| Carl Ebeling | 2 | 1405 | 185.32 |