Paper Info
Title
Design and Integration of Parallel Hough-Transform Chips for High-speed Line Detection
Abstract
Line detection is often needed in computer vision applications. The Hough transform processing of image data for line detection is robust but time-consuming. With the use of multiple processors, the processing time for Hough transform can be much reduced. In our research, we design an array processor for line-detection based on Hough transform that performs the line-parameter calculation and accumulation for different angles in parallel. Such an array processor together with its parallel peak extraction circuits have been implemented on a single chip. Based on the TSMC 0.35mum CMOS technology, the fabricated chip (with 10 processors) can be run successfully up to the clock rate of 50MHz. This paper presents the SOC design that can be extended to the integration of multiple chips to form a faster system with more parallel processors
Year
DOI
Venue
2005
10.1109/ICPADS.2005.126
ICPADS (2)
Keywords
Field
DocType
tsmc cmos technology,parallel peak extraction circuit,clock rate,parallel hough-transform chip design,parallel processing,cmos integrated circuits,parallel hough-transform chips,high-speed line detection,soc design,hough transform processing,parallel processor,line detection,array processor design,system-on-chip,multiple processor,array processor,multiple chip,single chip,integrated circuit design,computer vision,processing time,hough transforms,cmos technology,embedded system,process design,system on chip,circuits,robustness,chip,application software,hough transform
System on a chip,Computer science,Parallel computing,Hough transform,Real-time computing,Robustness (computer science),Chip,Integrated circuit design,Process design,Computer hardware,Vector processor,Clock rate
Conference
Volume
ISSN
ISBN
2
1521-9097
0-7695-2281-5
Citations 
PageRank 
References 
5
0.93
5
Authors
2
Name
Order
Citations
PageRank
Ming-Yang Chern110017.06
Yi-Hsiang Lu250.93