Paper Info
Title
Optimal speedup on a low-degree multi-core parallel architecture (LoPRAM)
Abstract
Over the last five years, major microprocessor manufacturers have released plans for a rapidly increasing number of cores per microprossesor, with upwards of 64 cores by 2015. In this setting, a sequential RAM computer will no longer accurately reflect the architecture on which algorithms are being executed. In this paper we propose a model of low degree parallelism (LoPRAM) which builds upon the RAM and PRAM models yet better reflects recent advances in parallel (multi-core) architectures. This model supports a high level of abstraction that simplifies the design and analysis of parallel programs. More importantly we show that in many instances it naturally leads to work-optimal parallel algorithms via simple modifications to sequential algorithms.
Year
DOI
Venue
2008
10.1145/1378533.1378568
SPAA
Keywords
Field
DocType
parallel algorithm,major microprocessor manufacturer,pram model,recent advance,sequential ram computer,optimal speedup,low degree parallelism,simple modification,low-degree multi-core parallel architecture,high level,parallel program,dynamic programming,divide and conquer,multi core,model of computation,models of computation,pram
Analysis of parallel algorithms,Cellular architecture,Parallel algorithm,Computer science,Parallel computing,Parallel programming model,Model of computation,Multi-core processor,Cost efficiency,Distributed computing,Speedup
Conference
Citations 
PageRank 
References 
8
0.48
17
Authors
3
Name
Order
Citations
PageRank
Reza Dorrigiv117614.02
Alejandro López-Ortiz21252107.44
Alejandro Salinger315112.53