Name
Abstract | ||
|---|---|---|
The current work introduces a method for predicting Memcached throughput on single-core and multi-core processors. The method is based on traces collected from a full system simulator running Memcached. A series of microarchitectural simulators consume these traces and the results are used to produce a CPI model composed of a baseline issue rate, cache miss rates, and branch misprediction rate. Simple queuing models are used to produce throughput predictions with accuracy in the range of 8% to 17%. |
Year | Venue | Keywords |
|---|---|---|
2012 | SpringSim (TMS-DEVS) | cpi model,baseline issue rate,branch misprediction rate,full system simulator,current work,microarchitectural simulator,memcached throughput,multi-core processor,throughput prediction |
Field | DocType | Volume |
Computer science,Parallel computing,Branch misprediction,Queueing theory,Cache miss,Throughput,Performance prediction | Conference | 44 |
Issue | ISSN | Citations |
4 | 0735-9276 | 8 |
PageRank | References | Authors |
0.51 | 6 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Steven Hart | 1 | 8 | 0.51 |
| Eitan Frachtenberg | 2 | 1060 | 85.08 |
| Mateusz Berezecki | 3 | 15 | 1.36 |