Paper Info
Title
Hardware Efficient Low-Latency Architecture for High Throughput Rate Viterbi Decoders
Abstract
By optimizing the number of look-ahead steps of the first layer of the previous low-latency architectures for M-step look-ahead high-throughput rate Viterbi decoders, this paper improves the hardware efficiency by large percentage with slight increase or even further decrease of the latency for the add-compare-select (ACS) computation. This is true especially when the encoder constraint length (K) is large. For example, when K = 7 and M varies from 21 to 84, 20.83% to 41.27% of the hardware cost in previous low latency Viterbi method can be saved with only up to 12% increase or 4% decrease of the latency of the conventional M-step look-ahead Viterbi decoder. The proposed architecture also relaxes the constraint on the look-ahead level M to be a multiple of K as was needed in the previous work. For example, when K = 7 and M (indivisible by K) varies from 40 to 80, 60.27% to 69.3% latency of conventional M-step look ahead Viterbi architecture can be reduced at the expense of 148.62% to 320.20% extra hardware complexity.
Year
DOI
Venue
2008
10.1109/TCSII.2008.2008061
IEEE Trans. on Circuits and Systems
Keywords
Field
DocType
low latency viterbi decoder,look-ahead implementation,hardware efficient low-latency architecture,hardware complexity,add-compare-select (acs),viterbi decoding,low latency viterbi decoder.,high throughput rate viterbi decoders,add-compare-select computation,high-throughput rate viterbi decoder,index terms—add-compare-select acs,look ahead,viterbi decoder,decoders,low latency,high throughput
Throughput (business),Computer science,Latency (engineering),Parallel computing,Look-ahead,Viterbi decoder,Encoder,Latency (engineering),Computer hardware,Viterbi algorithm,Computation
Journal
Volume
Issue
ISSN
55
12
1549-7747
Citations 
PageRank 
References 
6
0.68
6
Authors
2
Name
Order
Citations
PageRank
Chao Cheng1142.02
keshab k parhi23235369.07