Name
Abstract | ||
|---|---|---|
We describe the design and implementation of a packet-switched fiber optic interconnect prototype with a ShuffleNet topology, intended for use in shared-memory multiprocessors. Coupled with existing latency-hiding mechanisms, it can reduce latency to remote memory locations. Nodes use deflection routing to resolve contention. Each node contains a processor, memory, photonic switch, and packet routing processor. Payload remains in optical form from source to final destination. Each host processor is a commercial workstation with FIFO interfaces between its bus and the photonic switch. A global clock is distributed optically to each node to minimize skew. Component costs and network performance figures are presented for various node configurations including bit-per-wavelength and fiber-parallel packet formats. Our efforts to implement and test a practical interconnect including real host computers distinguishes our work from previous theoretical and experimental work. We summarize obstacles we encountered and discuss future work. |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1145/190314.190332 | SIGCOMM |
Keywords | Field | DocType |
network performance,fiber optic | FIFO (computing and electronics),Computer science,Network packet,Computer network,Burst switching,Workstation,Skew,Deflection routing,Payload,Network performance | Conference |
Volume | Issue | ISSN |
24 | 4 | 0146-4833 |
ISBN | Citations | PageRank |
0-89791-682-4 | 9 | 0.73 |
References | Authors | |
10 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| John R. Feehrer | 1 | 20 | 4.42 |
| Jon Sauer | 2 | 9 | 0.73 |
| Lars Ramfelt | 3 | 13 | 1.24 |