Name
Title | ||
|---|---|---|
A New Organization for a Perceptron-Based Branch Predictor and Its FPGA Implementation |
Abstract | ||
|---|---|---|
An unaltered rearrangement of the original computation of a neural based predictor at the algorithmic level is introduced as a new organization. Its FPGA implementation generates circuits that are 1.7 faster than a direct implementation of the original algorithm. This faster clock rate allows to implement predictors with longer history lengths using the nearly the same hardware budget. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ISVLSI.2005.11 | ISVLSI |
Keywords | Field | DocType |
original computation,hardware budget,fpga implementation,perceptron-based branch predictor,algorithmic level,new organization,direct implementation,unaltered rearrangement,faster clock rate,longer history length,original algorithm,modeling,prediction algorithms,accuracy,fpga,circuits,hardware,history,field programmable gate arrays | Computer science,Parallel computing,Field-programmable gate array,Electronic circuit,Perceptron,Clock rate,Branch predictor,Computation | Conference |
ISSN | ISBN | Citations |
2159-3477 | 0-7695-2365-X | 2 |
PageRank | References | Authors |
0.43 | 2 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Oswaldo Cadenas | 1 | 14 | 5.38 |
| Graham Megson | 2 | 13 | 4.03 |
| Daniel Jones | 3 | 2 | 0.43 |