Name
Abstract | ||
|---|---|---|
Transient or soft errors caused by various environmental effects are a growing concern in micro and nanoelectronics. We present a general framework for modeling and mitigating the logical effects of such errors in digital circuits. We observe that some errors have time-bounded effects; the system's output is corrupted for a few clock cycles, after which it recovers automatically. Since such erroneous behavior can be tolerated by some applications, i.e., it is noncritical at the system level, we define the critical soft error rate (CSER) as a more realistic alternative to the conventional SER measure. A simplified technology-independent fault model, the single transient fault (STF), is proposed for efficiently estimating the error probabilities associated with individual nodes in both combinational and sequential logic. STFs can be used to compute various other useful metrics for the faults and errors of interest, and the required computations can leverage the large body of existing methods and tools designed for (permanent) stuck-at faults. As an application of the proposed methodology, we introduce a systematic strategy for hardening logic circuits against transient faults. The goal is to achieve a desired level of CSER at minimum cost by selecting a subset of nodes for hardening against STFs. Exact and approximate algorithms to solve the node selection problem are presented. The effectiveness of this approach is demonstrated by experiments with the ISCAS-85 and -89 benchmark suites, as well as some large (multimillion-gate) industrial circuits. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/TDSC.2010.26 | IEEE Trans. Dependable Sec. Comput. |
Keywords | Field | DocType |
sequential logic,large body,system level,error tolerance,stuck-at fault,index terms—soft errors,hardening logic circuit,transient faults ✦,logic circuits,critical soft error rate,proposed methodology,mitigating transient errors,selective hardening,transient fault,soft error,single transient fault,indexing terms,microelectronics,error probability,digital circuits,computational modeling,fault model,logic gates,nanoelectronics,adders,logic circuit,combinational logic,stuck at fault | Stuck-at fault,Logic gate,Digital electronics,Sequential logic,Soft error,Computer science,Real-time computing,Combinational logic,Electronic circuit,Fault model | Journal |
Volume | Issue | ISSN |
8 | 4 | 1545-5971 |
Citations | PageRank | References |
21 | 0.93 | 30 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ilia Polian | 1 | 889 | 78.66 |
| J. P. Hayes | 2 | 3592 | 501.80 |
| Sudhakar M. Reddy | 3 | 5747 | 699.51 |
| Bernd Becker | 4 | 855 | 73.74 |