Name
Title | ||
|---|---|---|
Multi-logic-Unit processor: a combinational logic circuit evaluation engine for genetic parallel programming |
Abstract | ||
|---|---|---|
Genetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. GPP Logic Circuit Synthesizer (GPPLCS) is a combinational logic circuit learning system based on GPP. The GPPLCS comprises a Multi-Logic-Unit Processor (MLP) which is a hardware processor built on a Field Programmable Gate Array (FPGA). The MLP is designed to speed up the evaluation of genetic parallel programs that represent combinational logic circuits. Four combinational logic circuit problems are presented to show the performance of the hardware-assisted GPPLCS. Experimental results show that the hardware MLP speeds up evolutions over 10 times. For difficult problems such as the 6-bit priority selector and the 6-bit comparator, the speedup ratio can be up to 22. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1007/978-3-540-31989-4_15 | EuroGP |
Keywords | Field | DocType |
hardware processor,novel genetic programming paradigm,gpp logic circuit synthesizer,combinational logic circuit evaluation,combinational logic circuit,6-bit priority selector,genetic parallel programming,combinational logic circuit problem,6-bit comparator,multi-logic-unit processor,hardware-assisted gpplcs,hardware mlp speed,genetics,field programmable gate array | Logic gate,Sequential logic,Computer science,Logic optimization,Programmable logic array,Parallel computing,Field-programmable gate array,Combinational logic,Register-transfer level,Programmable logic device | Conference |
Volume | ISSN | ISBN |
3447 | 0302-9743 | 3-540-25436-6 |
Citations | PageRank | References |
2 | 0.50 | 12 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wai Shing Lau | 1 | 3 | 0.85 |
| Gang Li | 2 | 26 | 3.36 |
| Kin Hong Lee | 3 | 50 | 6.56 |
| Kwong-Sak Leung | 4 | 1887 | 205.58 |
| Sin Man Cheang | 5 | 44 | 5.14 |