Paper Info
Title
Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking
Abstract
Under current worst-case design practices, manufacturers specify conservative values for processor frequencies in order to guarantee correctness. To recover some of the lost performance and improve single-thread performance, this paper presents the Paceline leader-checker microarchitecture. In Paceline, a leader core runs the thread at higher-than-rated frequency, while passing execution hints and prefetches to a safely-clocked checker core in the same chip multiprocessor. The checker redundantly executes the thread faster than without the leader, while checking the results to guarantee correctness. Leader and checker cores periodically swap functionality. The result is that the thread improves performance substantially without significantly increasing the power density or the hardware design complexity of the chip. By overclocking the leader by 30%, we estimate that Paceline improves SPECint and SPECfp performance by a geometric mean of 21% and 9%, respectively. Moreover, Paceline also provides tolerance to transient faults such as soft errors.
Year
DOI
Venue
2007
10.1109/PACT.2007.52
PACT
Keywords
Field
DocType
current worst-case design practice,chip multiprocessor,single-thread performance,safely-clocked checker core,nanoscale cmps,leader core,specfp performance,checker redundantly,improving single-thread performance,checker core,lost performance,core overclocking,paceline leader-checker microarchitecture,chip,power density,geometric mean,soft error
Overclocking,Computer science,SPECfp,Parallel computing,Correctness,Thread (computing),Multiprocessing,Real-time computing,Chip,SPECint,Microarchitecture
Conference
ISSN
ISBN
Citations 
1089-795X
0-7695-2944-5
52
PageRank 
References 
Authors
1.95
19
2
Name
Order
Citations
PageRank
Brian Greskamp122910.92
Josep Torrellas23838262.89