Name
Title | ||
|---|---|---|
DEEP: an iterative fpga-based many-core emulation system for chip verification and architecture research |
Abstract | ||
|---|---|---|
This paper introduces the Delaware Enhanced Emulation Platform (DEEP) - a FPGA-based emulation system for hardware/software co-verification of many-core chip architectures. This platform exhibits the following three characteristics: fast compilation of logic designs, debugging support, and affordability. It is based on a novel iterative emulation methodology for hardware design and verification. We also conducted a logic design and integration of a new architectural feature that provides Full/Empty bit fine-grain synchronization for the IBM Cyclops-64 many-core architecture and evaluated its performance against existing synchronization constructs. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/1950413.1950438 | FPGA |
Keywords | Field | DocType |
chip verification,debugging support,many-core chip architecture,fpga-based emulation system,iterative fpga-based many-core emulation,synchronization construct,hardware design,architecture research,logic design,novel iterative emulation methodology,empty bit fine-grain synchronization,ibm cyclops-64 many-core architecture,delaware enhanced emulation platform,chip | Logic synthesis,Computer science,Real-time computing,Software,Hardware emulation,Synchronization,Computer architecture,Parallel computing,Field-programmable gate array,Semulation,Emulation,Embedded system,Debugging | Conference |
Citations | PageRank | References |
3 | 0.58 | 3 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Juergen Ributzka | 1 | 9 | 2.28 |
| Yuhei Hayashi | 2 | 3 | 0.91 |
| Fei Chen | 3 | 3 | 0.58 |
| Guang R. Gao | 4 | 2661 | 265.87 |