Name
Title | ||
|---|---|---|
Electronics and Telecommunications Research Institute: A Multiprocessor Server with a New Highly Pipelined Bus |
Abstract | ||
|---|---|---|
In this paper, we explore the design issues of a shared bus with pipelined protocol, so called HiPi+Bus, which is implemented for a multiprocessor server. The characteristics and design parameters for the HiPi+Bus are described. In the viewpoint of a pipelined bus, a block transfer is no good because of involving complex and unbalanced pipeline. However, it is requested by a local cache memory of which line size tends to be increased. To get the best performance and compensate unbalanced data transfer characteristic caused by block transfer, a responder queue for the bus interface is also proposed. According to the simulation results, it is explored that the HiPi+Bus, with help of the responder queue, can provide balanced service for more than 16 processors, which is important in running commercial applications. The HiPi+Bus is implemented for the TICOM III, a successor of the TICOM II which is the main server of the national administrative information network in Korea. |
Year | Venue | Keywords |
|---|---|---|
1996 | IPPS | ticom iii,pipelined bus,design parameter,shared bus,block transfer,main server,multiprocessor server,design issue,bus interface,ticom ii,responder queue,telecommunications research institute,new highly pipelined bus |
Field | DocType | ISBN |
Bus network,CPU cache,Computer science,Computer network,Address bus,Multiprocessing,Local bus,Back-side bus,System bus,Operating system,Control bus | Conference | 0-8186-7255-2 |
Citations | PageRank | References |
1 | 0.42 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Woojong Hahn | 1 | 17 | 2.98 |
| Ando Ki | 2 | 10 | 1.69 |
| Kee-Wook Rim | 3 | 154 | 24.20 |
| Soo-Won Kim | 4 | 116 | 29.86 |