Name
Abstract | ||
|---|---|---|
This paper presents a block turbo decoding algorithm, from its theory to its implementation in a programmable circuit. In this study, we discuss the two prototypes realized. It will be possible to compare the complexity of the core of the process, which is the elementary decoder, thanks to the choice of essential parameters. One prototype is more dedicated to high data rates, the other one being implemented on only one FPGA which means a gain in terms of area. First, we briefly focus on the description of the siso (Soft-In Soft-out) algorithm used to implement the turbo decoder Then, we explain the essential choices in order to adapt the algorithm for an ASIC implementation, which leads to a compromise between area and binary error rate. Finally, we present the two prototypes implemented and their experimental results. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1007/BF02995455 | ANNALES DES TELECOMMUNICATIONS-ANNALS OF TELECOMMUNICATIONS |
Keywords | Field | DocType |
error correcting code,turbo code,block code,decoding,ASIC,decoder,circuit design,circuit realization | Computer science,Turbo code,Block code,Circuit design,Field-programmable gate array,Error detection and correction,Electronic engineering,Application-specific integrated circuit,Decoding methods,Bit error rate | Journal |
Volume | Issue | ISSN |
56 | 7-8 | 0003-4347 |
Citations | PageRank | References |
5 | 0.71 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sylvie Kerouédan | 1 | 18 | 2.90 |
| Patrick Adde | 2 | 37 | 7.64 |
| Ramesh Pyndiah | 3 | 79 | 17.12 |