Name
Abstract | ||
|---|---|---|
Although communication fabrics at the microarchitectural level are mainly composed of standard primitives such as queues and arbiters, to get an executable model one has to connect these primitives with glue logic to complete the description. In this paper we identify a richer set of microarchitectural primitives that allows us to describe complete systems by composition alone. This enables us to build models faster (since models are now simply wiring diagrams at an appropriate level of abstraction) and to avoid common modeling errors such as inadvertent loss of data due to incorrect timing assumptions. Our models are formal and they are used for model checking as well as dynamic validation and performance modeling. However, unlike other formalisms this approach leads to a precise yet intuitive graphical notation for microarchitecture that captures timing and functionality in sufficient detail to be useful for reasoning about correctness and for communicating microarchitectural ideas to RTL and circuit designers and validators. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/HLDVT.2010.5496662 | 2010 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP (HLDVT) |
Keywords | Field | DocType |
formal verification,model error,switches,queues,mathematical model,microarchitecture,circuit design,data models,writing,model checking,circuits,logic | Data modeling,Model checking,Computer science,Correctness,Glue logic,Real-time computing,Rotation formalisms in three dimensions,Executable,Formal verification,Microarchitecture | Conference |
ISSN | Citations | PageRank |
1552-6674 | 24 | 1.27 |
References | Authors | |
13 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Satrajit Chatterjee | 1 | 258 | 15.65 |
| Michael Kishinevsky | 2 | 814 | 67.81 |
| Ümit Y. Ogras | 3 | 203 | 15.03 |