Title
Compact linear systolic arrays for multiplication using a trinomial basis in GF(2m) for high speed cryptographic processors
Abstract
Many of the cryptographic schemes over small characteristic finite fields are efficiently implemented by using a trinomial basis. In this paper, we present new linear systolic arrays for multiplication in GF(2m) for cryptographic applications using irreducible trinomials xm+xk+1. It is shown that our multipliers with trinomial basis require approximately 20 percent reduced hardware resources compared to previously proposed linear systolic multipliers using general irreducible polynomials. The proposed linear systolic arrays have the features of regularity and modularity, therefore, they are well suited to VLSI implementations.
Year
DOI
Venue
2005
10.1007/11424758_53
international conference on computational science and its applications
Keywords
Field
DocType
high speed cryptographic processor,hardware resource,cryptographic application,new linear systolic array,cryptographic scheme,proposed linear systolic array,linear systolic,trinomial basis,compact linear systolic array,irreducible trinomials xm,general irreducible polynomial,VLSI implementation
Discrete mathematics,Finite field,Polynomial,Systolic array,Arithmetic,Multiplier (economics),Multiplication,Very-large-scale integration,GF(2),Mathematics,Trinomial
Conference
Volume
ISSN
ISBN
3480
0302-9743
3-540-25860-4
Citations 
PageRank 
References 
1
0.36
8
Authors
3
Name
Order
Citations
PageRank
Soonhak Kwon117022.00
Chang Hoon Kim2739.02
Chun Pyo Hong3739.02