Title
A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC
Abstract
In Multi-Processor System-on-Chip (MPSoC) architectures equipped with shared-memory, caches have significant impact on performance and energy consumption. Indeed, if the executed application depicts a high degree of reference locality, caches may reduce the amount of shared-memory accesses and data transfers on the interconnection network. Hence, execution time and energy consumption can be greatly optimized. However, caches in MPSoC architectures put forward the data coherency problem. In this context, most of the existing solutions are based either on data invalidation or data update protocols. These protocols do not consider the change in the application behavior. This paper presents a new hybrid cache-coherency protocol that is able to dynamically adapt its functioning mode according to the application needs. An original architecture which facilitates this protocol's implementation in Network-On-Chip based MPSoC architectures is also proposed. Performances, in terms of speed up factor and energy reduction gain of the proposed protocol, have been evaluated using a Cycle Accurate Bit Accurate (CABA) simulation platform. Experimental results in comparison with other existing solutions show that this protocol may give significant reductions in execution time and energy consumption can be achieved.
Year
DOI
Venue
2009
10.1109/DSD.2009.220
DSD
Keywords
Field
DocType
dynamic hybrid cache coherency,shared-memory mpsoc,protocols,network on chip,data mining,computer architecture,cache coherence,radiation detectors,data transfer,coherence,shared memory
Shared memory,MESIF protocol,Computer science,Parallel computing,Network on a chip,Real-time computing,Interconnection,Energy consumption,MPSoC,Embedded system,Cache coherence,Speedup
Conference
Citations 
PageRank 
References 
1
0.38
14
Authors
5
Name
Order
Citations
PageRank
Hajer Chtioui110.38
Rabie Ben Atitallah217320.23
Smail Niar313112.29
Jean-luc Dekeyser443353.54
Mohamed Abid55818.25