Paper Info
Title
Real time fractal image coder based on characteristic vector matching
Abstract
Fractal coding algorithm has many applications including image compression. In this paper a classification scheme is presented which allows the hardware implementation of the fractal coder. High speed and low power consumption are the goal of the suggested design. The introduced method is based on binary classification of domain and range blocks. The proposed technique increases the processing speed and reduces the power consumption while the qualities of the reconstructed images are comparable with those of the available software techniques. In order to show the functionality of the proposed algorithm, the architecture was implemented on a FPGA chip. The application of the proposed hardware is shown in image compression. The resulted compression ratios, PSNR error, gate count, compression speed and power consumption are compared with the existing designs. Other applications of the proposed design are feasible in certain fields such as mass-volume database coding and also in video coder's block matching schemes.
Year
DOI
Venue
2010
10.1016/j.imavis.2010.03.011
Image Vision Comput.
Keywords
Field
DocType
fractal image compression,proposed hardware,compression speed,low power consumption,power consumption,high speed,proposed algorithm,compression ratio,classification,proposed technique,image compression,characteristic vector matching,low power,real time fractal image,proposed design,binary classification,real time,chip
Gate count,Binary classification,Fractal compression,Computer science,Real-time computing,Artificial intelligence,Computer vision,Data compression ratio,Fractal,Algorithm,Compression ratio,Data compression,Image compression
Journal
Volume
Issue
ISSN
28
11
Image and Vision Computing
Citations 
PageRank 
References 
4
0.45
21
Authors
4
Name
Order
Citations
PageRank
S. Samavi1565.49
M. Habibi2185.69
S. Shirani330125.69
N. Rowshanbin440.45