Name
Abstract | ||
|---|---|---|
A methodology is presented for the synthesis of analog circuits using piecewise linear (PWL) approximations. The function to be synthesized is divided into PWL segments such that each segment can be realized using elementary MOS current-mode programmable-gain circuits. A number of these elementary current-mode circuits when connected in parallel, it is possible to realize piecewise linear approximation of any arbitrary analog function with in the allowed approximation error bounds. Simulation results show a close agreement between the desired function and the synthesized output. The number of PWL segments used for approximation and hence the circuit area is determined by the required accuracy and the smoothness of the resulting function. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/VLSID.2006.88 | VLSI Design |
Keywords | Field | DocType |
elementary mos current-mode programmable-gain,arbitrary analog function,extrinsic analog,approximation error bound,analog circuit,piecewise linear approximation,synthesized output,pwl segment,piecewise linear current-mode circuits,circuit area,elementary current-mode circuit,resulting function,network synthesis,approximation error,analog circuits,piecewise linear | Analogue electronics,Analog synthesis,Network synthesis filters,Electronic engineering,Electronic circuit,Current mode,Smoothness,Piecewise linear function,Approximation error,Mathematics | Conference |
ISSN | ISBN | Citations |
1063-9667 | 0-7695-2502-4 | 4 |
PageRank | References | Authors |
0.65 | 10 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. S. Bhat | 1 | 22 | 3.59 |
| S. Rekha | 2 | 8 | 5.62 |
| H. S. Jamadagni | 3 | 160 | 30.14 |