Name
Abstract | ||
|---|---|---|
The paper presents a method of settling time minimization in switched capacitor (SC) circuits. This problem has been discussed in recent papers because of high-frequency applications of SC networks. In comparison with the methods elaborated up to now and limited to biquads, the method presented in this paper can be used for an SC circuit containing an arbitrary number of operational amplifiers coupled together in each switching state and modelled as ideal transconductances. The fifth-order ladder bilinear SC filter is considered for illustration of the method and SPICE simulations. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1002/cta.4490230409 | INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS |
Keywords | Field | DocType |
symbolic analysis | Settling time,Spice,Computer science,Electronic engineering,Switched capacitor,Symbolic data analysis,Network analysis,Electronic circuit,Operational amplifier,Bilinear interpolation | Journal |
Volume | Issue | ISSN |
23 | 4 | 0098-9886 |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Andrzej Handkiewicz | 1 | 11 | 2.44 |
| Pawel Śniatala | 2 | 0 | 0.34 |