Name
Abstract | ||
|---|---|---|
This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25-µm complementary metal-oxide-semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb/s over 5-10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5-48.7-mW power dissipation was measured for signal activity above 0.1, equivalent to 0.80-1.52 pJ/b. This work demonstrates a 15.0%-67.5% power reduction over a conventional single-ended voltage-mode static bus while reducing delay latency by 28.3% and peak current by 70%. The proposed bus architecture is robust against crosstalk noise and occupies comparable routing area to a reference static bus design. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/TVLSI.2008.2002682 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
differential current-mode bus architecture,lossy interconnects,power reduction,power dissipation,on-chip bus,16-b bus core,bus power dissipation,proposed bus architecture,single-ended voltage-mode static bus,delay latency,reference static bus design,cmos technology,voltage,energy efficiency,repeaters,power transmission lines,complementary metal oxide semiconductor,propagation delay,chip,bandwidth,pre emphasis | Propagation delay,Computer science,IEBus,Electronic engineering,Electric power transmission,CMOS,Slack bus,Emphasis (telecommunications),Repeater,Electrical engineering,Low-power electronics | Journal |
Volume | Issue | ISSN |
17 | 9 | 1063-8210 |
Citations | PageRank | References |
6 | 1.23 | 7 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Liang Zhang | 1 | 23 | 3.63 |
| John M. Wilson | 2 | 118 | 11.79 |
| Rizwan Bashirullah | 3 | 200 | 42.61 |
| Lei Luo | 4 | 56 | 12.41 |
| Jian Xu | 5 | 309 | 21.80 |
| Paul D. Franzon | 6 | 634 | 83.24 |