Title
A low – power VLSI architecture for intra prediction in h.264
Abstract
The H.264 video coding standard can achieve considerably higher coding efficiency than previous standards. The key to this high code efficiency are mainly the Intra and Inter prediction modes provided by the standard. However, the compression efficiency of the H264 standard comes at the cost of increased complexity of the encoder. Therefore it is very important to design video architectures that minimize the cost of the prediction modes in terms of area, power dissipation and design complexity. A common aspect of the Inter and Intra Prediction modes, is the Sum of Absolute Differences (SAD). In this paper we present a new algorithm that can replace the SAD in Intra Prediction, and which provides a more efficient hardware implementation.
Year
DOI
Venue
2005
10.1007/11573036_60
Panhellenic Conference on Informatics
Keywords
Field
DocType
power dissipation
Algorithmic efficiency,Dissipation,Computer science,Image coding,Real-time computing,Coding (social sciences),Encoder,Sum of absolute differences,Vlsi architecture
Conference
ISBN
Citations 
PageRank 
3-540-29673-5
0
0.34
References 
Authors
2
4
Name
Order
Citations
PageRank
Georgios Stamoulis1116.11
Maria G. Koziri2258.46
Ioannis Katsavounidis3887.63
Nikolaos Bellas422023.30