Name
Abstract | ||
|---|---|---|
This paper addresses an open-source UML based toolkit - named TTool - for performing efficient system-level design space exploration of Systems-On-Chip. Main modeling, verification and simulation capabilities of TTool are first presented, and exemplified by an MPEG2 application. Then, an innovative simulation strategy to significantly reduce simulation time is introduced. The basic idea is to take benefit from high level descriptions of applications by processing transactions spanning potentially hundreds of clock cycles as a whole. When a need for inter task synchronization arises, transactions may be split into smaller chunks. The simulation engine is therefore predictive and supports backward execution thanks to transaction truncation. Thus, simulation granularity adapts automatically to application requirements. Emphasis is more particularly put on procedures taking place under the hood after having pushed the Wool simulation button. Finally, the new simulation strategy is assessed and compared to an earlier cycle-based version of the simulation engine. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1007/978-3-642-02571-6_18 | Lecture Notes in Business Information Processing |
Keywords | Field | DocType |
System-On-Chip,Design Space Exploration,System Level Modeling,UML,DIPLODOCUS,TTool,Fast Simulation Techniques | Truncation,Synchronization,System level modeling,System on a chip,Unified Modeling Language,Computer science,Granularity,Database transaction,Design space exploration,Embedded system | Conference |
Volume | ISSN | Citations |
33 | 1865-1348 | 5 |
PageRank | References | Authors |
0.73 | 12 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daniel Knorreck | 1 | 33 | 2.72 |
| Ludovic Apvrille | 2 | 136 | 22.23 |
| Renaud Pacalet | 3 | 260 | 24.51 |