Title
The cascaded predictor: economical and adaptive branch target prediction
Abstract
this paper use a total path length of 24bits). The lower-order branch address bits are xor-ed with thispattern, resulting in a 24-bit key pattern. Two-level predictorswith longer path lengths use fewer bits of each target address,so that the length of the pattern remains constant. Forexample, a path length 6 predictor uses 4 bits from each targetaddress. Note that a two-level predictor with path length 0reverts to a BTB. The 24-bit key pattern is used, as in a BTB,to access the...
Year
DOI
Venue
1998
10.1109/MICRO.1998.742786
MICRO
Keywords
Field
DocType
cascaded predictor,adaptive branch target prediction,computer architecture
Indirect branch,Working set,Computer science,Parallel computing,Branch target predictor,Real-time computing,Cold start (automotive),Branch predictor
Conference
ISSN
ISBN
Citations 
1072-4451
1-58113-016-3
45
PageRank 
References 
Authors
2.98
13
2
Name
Order
Citations
PageRank
Karel Driesen120516.32
Urs Hölzle23492346.29