Name
Abstract | ||
|---|---|---|
The syntax-directed synthesis paradigm has shown to be a powerful synthesis approach. However, its control-driven nature results in significant performance overhead. Some methods to reduce this overhead include peephole optimisations, control resynthesis and component optimisations. This work explores new methods of improving the performance of syntax-directed synthesised asynchronous circuits, using the Balsa synthesis system as the research framework. This includes investigating description styles and the usage of language constructs that exploit the directness of the synthesis method to obtain more concurrent and faster circuits. The techniques and optimisations presented here has been tested in a set of non-trivial examples including a 32-bit processor, a Viterbi decoder, and a channel-sliced wormhole router. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/DSD.2010.71 | DSD |
Keywords | Field | DocType |
synthesisable asynchronous circuits,32-bit processor,peephole optimisations,significant performance overhead,description-level optimisation,component optimisations,powerful synthesis approach,syntax-directed synthesised asynchronous circuit,syntax-directed synthesis paradigm,viterbi decoder,balsa synthesis system,synthesis method,optimization,decoding,research framework,registers,32 bit processor,logic design,asynchronous circuit,integrated circuits,broadcasting | 32-bit,Logic synthesis,Asynchronous communication,Computer science,Parallel computing,Language construct,Real-time computing,Exploit,Viterbi decoder,Decoding methods,Integrated circuit | Conference |
Citations | PageRank | References |
1 | 0.41 | 4 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Luis A. Tarazona | 1 | 5 | 1.05 |
| Doug A. Edwards | 2 | 5 | 1.32 |
| Andrew Bardsley | 3 | 7 | 1.58 |
| L. A. Plana | 4 | 786 | 59.01 |