Name
Abstract | ||
|---|---|---|
The Scalable Communications Core (SCC) is a power- and area-efficient solution for physical layer (PHY) and lower MAC processing of concurrent multiple wireless protocols. Our architecture consists of coarse-grained, heterogeneous, programmable accelerators ... |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ISVLSI.2007.3 | ISVLSI |
Keywords | Field | DocType |
low power architecture,digital delay measurement,lower mac processing,physical layer,concurrent multiple wireless protocol,area-efficient solution,scalable communications core,programmable accelerator,registers,integrated circuit design,digital signals,low power electronics,synchronization,computer architecture,power dissipation | Synchronization,Digital signal,Dissipation,Delay,Electronic engineering,Integrated circuit design,Engineering,Energy consumption,Electrical engineering,Low-power electronics | Conference |
ISSN | ISBN | Citations |
2159-3469 | 0-7695-2896-1 | 0 |
PageRank | References | Authors |
0.34 | 5 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Franco Martin-Pirchio | 1 | 0 | 0.34 |
| Alfonso Chacon-rodriguez | 2 | 8 | 5.53 |
| Pedro Julian | 3 | 11 | 4.41 |
| Pablo Mandolesi | 4 | 0 | 0.34 |
| Martin-Pirchio, F. | 5 | 0 | 0.34 |
| Chacon-Rodriguez, A. | 6 | 0 | 0.34 |